Known in the art is chip (integrated circuit (IC)) stacking technology which may include using multiple technology nodes requiring multiple voltages. One way of supplementing current and localized voltage on a chip or within a chip stack is by using on-chip decoupling capacitors (commonly referred to as “decaps”) such as deep trench or parallel plate structures. A problem with typical on chip decoupling capacitors is the area (which is expensive real estate) required for any significant decoupling capacitance, as well as the ability to place the capacitance where it is needed, and at the correct voltage for a die with multiple voltage levels versus location and area utilized for active circuits. Off chip decoupling capacitors may be used, however, a problem for off chip decoupling capacitors is that they become less effective the greater the distance they are away from the chip which can be impacted by their effective inductance and the frequency of the chip and circuit simultaneous switching. In addition, when considering a multiple high chip stacking technology, it is difficult to integrate the appropriate, power supply, voltage supply & distribution, with low cost, low inductance decoupling capacitors into a 3D working chip stack. Further, it is difficult to achieve proper integration while also considering integration of power distribution, high bandwidth interconnections, multiple circuits switching simultaneously and voltage variations within tight distributions for proper circuit operations.
It would therefore be desirable to provide or supplement a particular voltage within a 3D chip stack or package and maintain a low inductance capacitor locally and help control the voltage variations within a chip, 3D chip stack or for multiple chips in a package.